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D! 1[^_]ËCdD$*$D$%CtD$*$D$ CpD$(+$D$!UWVS] C{ D$.D$D$.D$0.$D$ st01ۍt&DD$ ߃D$ .$D$r9uփ1[^_]ÐUVS] DFD$D$$X.D$ C D$1D$D$ DF$CD$1D$D$ DF$CD$1D$D$ DF$CD$ 2D$D$ DF$bCD$D2D$D$ DF$>C D$h2D$D$ DF$C$D$2D$D$ DF$C(D$2D$D$ DF$C,D$2D$D$ DF$C0D$2D$D$ DF$C4D$3D$D$ DF$fC8D$@3D$D$ DF$BChpF@BlMAC Registers enableddisabledresetbiglittle10Mb/s100Mb/s1000Mb/sno link configPCI Express64-bit32-bit100MHz66MHz133MHzPCI-Xdon't passignoredfilteredacceptignore1/21/41/8reserved163848192409620481024512256M88IGPIGP2unknownPCI0x00000: CTRL (Device control register) 0x%08X Endian mode (buffers): %s Link reset: %s Set link up: %s Invert Loss-Of-Signal: %s Receive flow control: %s Transmit flow control: %s VLAN mode: %s Auto speed detect: %s Speed select: %s Force speed: %s Force duplex: %s 0x00008: STATUS (Device status register) 0x%08X Duplex: %s Link up: %s TBI mode: %s Link speed: %s Bus type: %s Port number: %s TBI mode: %s Link speed: %s Bus type: %s Bus speed: %s Bus width: %s 0x00100: RCTL (Receive control register) 0x%08X Receiver: %s Store bad packets: %s Unicast promiscuous: %s Multicast promiscuous: %s Long packet: %s Descriptor minimum threshold size: %s Broadcast accept mode: %s VLAN filter: %s Canonical form indicator: %s Discard pause frames: %s Pass MAC control frames: %s Receive buffer size: %s 0x02808: RDLEN (Receive desc length) 0x%08X 0x02810: RDH (Receive desc head) 0x%08X 0x02818: RDT (Receive desc tail) 0x%08X 0x02820: RDTR (Receive delay timer) 0x%08X 0x00400: TCTL (Transmit ctrl register) 0x%08X Transmitter: %s Pad short packets: %s Software XOFF Transmission: %s Re-transmit on late collision: %s 0x03808: TDLEN (Transmit desc length) 0x%08X 0x03810: TDH (Transmit desc head) 0x%08X 0x03818: TDT (Transmit desc tail) 0x%08X 0x03820: TIDV (Transmit delay timer) 0x%08X PHY type: %s UEEEE55&&&eeeeuueueaddr_low0x%04lx: %-16s 0x%08x addr_highhash_table_highhash_table_lowr_des_startx_des_startr_buff_sizeecntrlieventimaskivecr_des_activex_des_activemii_datamii_speedr_boundr_fstartx_fstartfun_coder_cntrlr_hashx_cntrlMAL%d Registers TX| CTP%d = 0x%08x RX|RCBS%d = 0x%08x (%d) EMAC%d Registers IPCR = 0x%08x ZMII%d Registers RGMII%d Registers FER = %08x SSR = %08x TAH%d Registers CFG = 0x%08x ESR = 0x%08x IER = 0x%08x TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x MR0 = 0x%08x MR1 = 0x%08x RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x TRTR = 0x%08x RWMR = 0x%08x IAR = %04x%08x LSA = %04x%08x IAHT = 0x%04x 0x%04x 0x%04x 0x%04x GAHT = 0x%04x 0x%04x 0x%04x 0x%04x VTPID = 0x%04x VTCI = 0x%04x IPGVR = 0x%04x STACR = 0x%08x OCTX = 0x%08x OCRX = 0x%08x FER = %08x SSR = %08x SMIISR = %08x REVID = %08x MR = %08x TSR = %08x SSR0 = %08x SSR1 = %08x SSR2 = %08x SSR3 = %08x SSR4 = %08x SSR5 = %08x 0x00000: CTRL0 (Device control register) 0x%08X Link reset: %s VLAN mode: %s 0x00010: STATUS (Device status register) 0x%08X Link up: %s Bus type: %s Bus speed: %s Bus width: %s 0x00100: RCTL (Receive control register) 0x%08X Receiver: %s Store bad packets: %s Unicast promiscuous: %s Multicast promiscuous: %s Descriptor minimum threshold size: %s Broadcast accept mode: %s VLAN filter: %s Cononical form indicator: %s 0x00120: RDLEN (Receive desc length) 0x%08X 0x00128: RDH (Receive desc head) 0x%08X 0x00130: RDT (Receive desc tail) 0x%08X 0x00138: RDTR (Receive delay timer) 0x%08X 0x00600: TCTL (Transmit ctrl register) 0x%08X Transmitter: %s 0x00610: TDLEN (Transmit desc length) 0x%08X 0x00618: TDH (Transmit desc head) 0x%08X 0x00620: TDT (Transmit desc tail) 0x%08X 0x00628: TIDV (Transmit delay timer) 0x%08X %s Interrupt: %s Address Data ------- ------ 0x%02x 0x%04x Mac/BIU Registers Active Reset In Progress UpDownReversedNormalNot DoneNot Half/Full10/100AdvertiseIn ProgressFailedPassedRx CompleteRx DescriptorRx Packet ErrorRx Early ThresholdRx IdleRx OverrunTx Packet OKTx DescriptorTx Packet ErrorTx IdleTx UnderrunMIB ServiceSoftwarePower Management EventPhyHigh Bits ErrorRx Status FIFO OverrunReceived Target AbortReceived Master AbortSignaled System ErrorDetected Parity ErrorRx Reset CompleteTx Reset Complete No Interrupts Active Masked Interrupts %s AcceptedRejected Wake on Arp Enabled SecureOn Hack Detected Phy Interrupt Received Arp Received Pattern 0 Received Pattern 1 Received Pattern 2 Received Pattern 3 Received Magic Packet Received Counters Frozen Value = %d Internal Phy Registers ---------------------- Port Isolated Loopback Enabled Remote Fault Detected Advertising 100Base-T4 Advertising Pause Next Page Desired Supports 100Base-T4 Supports Pause Indicates Remote Fault Reverse MII Interrupt Detected False Carrier Detected Rx Error Detected MII Interrupts %s MII Interrupt Pending BypassedFree-RunningPhase-AdjustedForcedEnhancedReducedFailed or Not Run'Magic' Phy Registers ForceDetectedMagic number 0x%08x does not match 0x%08x 0x00: CR (Command): 0x%08x Transmit %s Receive %s 0x04: CFG (Configuration): 0x%08x %s Endian Boot ROM %s Internal Phy %s Phy Reset %s External Phy %s Default Auto-Negotiation %s, %s %s Mb %s Duplex Phy Interrupt %sAuto-Cleared Phy Configuration = 0x%02x Auto-Negotiation %s %s Polarity %s Duplex %d Mb/s Link %s 0x08: MEAR (EEPROM Access): 0x%08x 0x0c: PTSCR (PCI Test Control): 0x%08x EEPROM Self Test %s Rx Filter Self Test %s Tx FIFO Self Test %s Rx FIFO Self Test %s EEPROM Reload In Progress 0x10: ISR (Interrupt Status): 0x%08x 0x14: IMR (Interrupt Mask): 0x%08x 0x18: IER (Interrupt Enable): 0x%08x 0x20: TXDP (Tx Descriptor Pointer): 0x%08x 0x24: TXCFG (Tx Config): 0x%08x Drain Threshhold = %d bytes (%d) Fill Threshhold = %d bytes (%d) Max DMA Burst per Tx = %d bytes Automatic Tx Padding %s Mac Loopback %s Heartbeat Ignore %s Carrier Sense Ignore %s 0x30: RXDP (Rx Descriptor Pointer): 0x%08x 0x34: RXCFG (Rx Config): 0x%08x Drain Threshhold = %d bytes (%d) Max DMA Burst per Rx = %d bytes Long Packets %s Tx Packets %s Runt Packets %s Error Packets %s 0x3c: CCSR (CLKRUN Control/Status): 0x%08x CLKRUNN %s Power Management %s Power Management Event Pending 0x40: WCSR (Wake-on-LAN Control/Status): 0x%08x Wake on Phy Interrupt Enabled Wake on Unicast Packet Enabled Wake on Multicast Packet Enabled Wake on Broadcast Packet Enabled Wake on Pattern 0 Match Enabled Wake on Pattern 1 Match Enabled Wake on Pattern 2 Match Enabled Wake on Pattern 3 Match Enabled Wake on Magic Packet Enabled Magic Packet SecureOn Enabled Unicast Packet Received Multicast Packet Received Broadcast Packet Received 0x44: PCR (Pause Control/Status): 0x%08x Pause Counter = %d Pause %sNegotiated Pause on DA %s Pause on Mulitcast %s Pause %s PS_RCVD: Pause Frame Received 0x48: RFCR (Rx Filter Control): 0x%08x Unicast Hash %s Multicast Hash %s Arp %s Pattern 0 Match %s Pattern 1 Match %s Pattern 2 Match %s Pattern 3 Match %s Perfect Match %s All Unicast %s All Multicast %s All Broadcast %s Rx Filter %s 0x4c: RFDR (Rx Filter Data): 0x%08x PMATCH 1-0 = 0x%08x PMATCH 3-2 = 0x%08x PMATCH 5-4 = 0x%08x PCOUNT 1-0 = 0x%08x PCOUNT 3-2 = 0x%08x SOPASS 1-0 = 0x%08x SOPASS 3-2 = 0x%08x SOPASS 5-4 = 0x%08x 0x50: BRAR (Boot ROM Address): 0x%08x Automatically Increment Address 0x54: BRDR (Boot ROM Data): 0x%08x 0x58: SRR (Silicon Revision): 0x%08x 0x5c: MIBC (Mgmt Info Base Control): 0x%08x Counter Overflow Warning 0x60: MIB[0] (Rx Errored Packets): 0x%04x 0x64: MIB[1] (Rx Frame Sequence Errors): 0x%02x 0x68: MIB[2] (Rx Missed Packets): 0x%02x 0x6c: MIB[3] (Rx Alignment Errors): 0x%02x 0x70: MIB[4] (Rx Symbol Errors): 0x%02x 0x74: MIB[5] (Rx Long Frame Errors): 0x%02x 0x78: MIB[6] (Tx Heartbeat Errors): 0x%02x 0x80: BMCR (Basic Mode Control): 0x%04x %s Duplex Port is Powered %s Auto-Negotiation %s %d Mb/s Auto-Negotiation Restarting 0x84: BMSR (Basic Mode Status): 0x%04x Link %s %sCapable of Auto-Negotiation Auto-Negotiation %sComplete %sCapable of Preamble Suppression %sCapable of 10Base-T Half Duplex %sCapable of 10Base-T Full Duplex %sCapable of 100Base-TX Half Duplex %sCapable of 100Base-TX Full Duplex %sCapable of 100Base-T4 Jabber Condition Detected 0x88: PHYIDR1 (PHY ID #1): 0x%04x 0x8c: PHYIDR2 (PHY ID #2): 0x%04x OUI = 0x%06x Model = 0x%02x (%d) Revision = 0x%01x (%d) 0x90: ANAR (Autoneg Advertising): 0x%04x Protocol Selector = 0x%02x (%d) Advertising 10Base-T Half Duplex Advertising 10Base-T Full Duplex Advertising 100Base-TX Half Duplex Advertising 100Base-TX Full Duplex Indicating Remote Fault 0x94: ANLPAR (Autoneg Partner): 0x%04x Supports 10Base-T Half Duplex Supports 10Base-T Full Duplex Supports 100Base-TX Half Duplex Supports 100Base-TX Full Duplex Indicates Acknowledgement 0x98: ANER (Autoneg Expansion): 0x%04x Link Partner Can %sAuto-Negotiate Link Code Word %sReceived Next Page %sSupported Link Partner Next Page %sSupported Parallel Detection Fault 0x9c: ANNPTR (Autoneg Next Page Tx): 0x%04x 0xc0: PHYSTS (Phy Status): 0x%04x Link %s %d Mb/s %s Duplex Auto-Negotiation %sComplete %s Polarity 0xc4: MICR (MII Interrupt Control): 0x%04x 0xc8: MISR (MII Interrupt Status): 0x%04x Rx Error Counter Half-Full Interrupt %s False Carrier Counter Half-Full Interrupt %s Auto-Negotiation Complete Interrupt %s Remote Fault Interrupt %s Jabber Interrupt %s Link Change Interrupt %s 0xcc: PGSEL (Phy Register Page Select): 0x%04x 0xd0: FCSCR (False Carrier Counter): 0x%04x 0xd4: RECR (Rx Error Counter): 0x%04x 0xd8: PCSR (100Mb/s PCS Config/Status): 0x%04x NRZI Bypass %s %s Signal Detect Algorithm %s Signal Detect Operation True Quiet Mode %s Rx Clock is %s 4B/5B Operation %s Forced 100 Mb/s Good Link 0xe4: PHYCR (Phy Control): 0x%04x Phy Address = 0x%x (%d) %sPause Compatible with Link Partner LED Stretching %s Phy Self Test %s Self Test Sequence = PSR%d 0xe8: TBTSCR (10Base-T Status/Control): 0x%04x Jabber %s Heartbeat %s Polarity Auto-Sense/Correct %s %s Polarity %s Normal Link Pulse %s 10 Mb/s Loopback %s Forced 10 Mb/s Good Link 0xe4: PMDCSR: 0x%04x 0xf4: DSPCFG: 0x%04x 0xf8: SDCFG: 0x%04x 0xfc: TSTDAT: 0x%04x Driver: %s Version: %s APROM: %04x CSR%02d: BCR%02d: MII%02d: BABL CERR MISS MERR RINT IDON INTR RXON TXON TDMD STOP INIT BABLM MISSM MERRM RINTM TINTM IDONM DXSUFLO LAPPEN DXMT2PD EMBA BSWP EN124 DMAPLUS TXDPOLL APAD_XMT ASTRP_RCV MFCO MFCON UINTCMD UINT RCVCCO RCVCCOM TXSTRT TXSTRTM JAB JABM TOKINTD LTINTEN SINT SINTE SLPINT SLPINTE EXDINT EXDINTE MPPLBA MPINT MPINTE MPEN MPMODE SPND FASTSPNDE RXFRTG RDMD RXDPOLL STINT STINTE MREINT MREINTE MAPINT MAPINTE MCCINT MCCINTE MCCIINT MCCIINTE MIIPDTINT MIIPDTINTE PCnet/PCI 79C970 PCnet/PCI II 79C970A PCnet/FAST 79C971 PCnet/FAST+ 79C972 PCnet/FAST III 79C973 PCnet/Home 79C978 PCnet/FAST III 79C975 PCnet/PRO 79C976VER: %04x PARTIDU: %04x TMAULOOP LEDPE APROMWE INTLEVEL EADISEL AWAKE ASEL XMAUSEL PVALID EEDET CSR0: Status and Control 0x%04x CSR3: Interrupt Mask 0x%04x CSR4: Test and Features 0x%04x CSR5: Ext Control and Int 1 0x%04x CSR7: Ext Control and Int 2 0x%04x CSR15: Mode 0x%04x CSR40: Current RX Byte Count 0x%04x CSR41: Current RX Status 0x%04x CSR42: Current TX Byte Count 0x%04x CSR43: Current TX Status 0x%04x CSR88: Chip ID Lower 0x%04x CSR89: Chip ID Upper 0x%04x CSR112: Missed Frame Count 0x%04x CSR114: RX Collision Count 0x%04x BCR2: Misc. Configuration 0x%04x BCR9: Full-Duplex Control 0x%04x BCR18: Burst and Bus Control 0x%04x BCR19: EEPROM Control and Status 0x%04x BCR23: PCI Subsystem Vendor ID 0x%04x BCR24: PCI Subsystem ID 0x%04x BCR31: Software Timer 0x%04x BCR32: MII Control and Status 0x%04x BCR35: PCI Vendor ID 0x%04x RxErr TxErr RxNoBuf LinkChg RxFIFO TxNoBuf SWInt TimeOut SERR %s%s%s%s%s%s%s%s%s%s%s unknown RealTek chip ERxOK ERxOverWrite ERxBad ERxGood %s%s%s%s , RESET Big-endian mode Home LAN enable VLAN de-tagging RX checksumming PCI 64-bit DAC PCI Multiple RW RTL-8139RTL-8139-KRTL-8139ARTL-8139A-GRTL-8139BRTL-8130RTL-8139CRTL-8100RTL-8100B/8139DRTL-8139C+RTL-8101RTL-8168B/8111BRTL-8101ERTL-8169RTL-8169sRTL-8110RealTek %s registers: ------------------------------ 0x00: MAC Address %02x:%02x:%02x:%02x:%02x:%02x 0x08: Multicast Address Filter 0x%08x 0x%08x 0x10: Dump Tally Counter Command 0x%08x 0x%08x 0x20: Tx Normal Priority Ring Addr 0x%08x 0x%08x 0x28: Tx High Priority Ring Addr 0x%08x 0x%08x 0x10: Transmit Status Desc 0 0x%08x 0x14: Transmit Status Desc 1 0x%08x 0x18: Transmit Status Desc 2 0x%08x 0x1C: Transmit Status Desc 3 0x%08x 0x20: Transmit Start Addr 0 0x%08x 0x24: Transmit Start Addr 1 0x%08x 0x28: Transmit Start Addr 2 0x%08x 0x2C: Transmit Start Addr 3 0x%08x 0x30: Flash memory read/write 0x%08x 0x30: Rx buffer addr (C mode) 0x%08x 0x34: Early Rx Byte Count %8u 0x36: Early Rx Status 0x%02x 0x37: Command 0x%02x Rx %s, Tx %s%s 0x38: Current Address of Packet Read (C mode) 0x%04x 0x3A: Current Rx buffer address (C mode) 0x%04x 0x3C: Interrupt Mask 0x%04x 0x3E: Interrupt Status 0x%04x 0x40: Tx Configuration 0x%08x 0x44: Rx Configuration 0x%08x 0x48: Timer count 0x%08x 0x4C: Missed packet counter 0x%06x 0x50: EEPROM Command 0x%02x 0x51: Config 0 0x%02x 0x52: Config 1 0x%02x 0x53: Config 2 0x%02x 0x54: Config 3 0x%02x 0x55: Config 4 0x%02x 0x56: Config 5 0x%02x 0x58: Timer interrupt 0x%08x 0x5C: Multiple Interrupt Select 0x%04x 0x60: PHY access 0x%08x 0x64: TBI control and status 0x%08x 0x68: TBI Autonegotiation advertisement (ANAR) 0x%04x 0x6A: TBI Link partner ability (LPAR) 0x%04x 0x6C: PHY status 0x%02x 0x84: PM wakeup frame 0 0x%08x 0x%08x 0x8C: PM wakeup frame 1 0x%08x 0x%08x 0x94: PM wakeup frame 2 (low) 0x%08x 0x%08x 0x9C: PM wakeup frame 2 (high) 0x%08x 0x%08x 0xA4: PM wakeup frame 3 (low) 0x%08x 0x%08x 0xAC: PM wakeup frame 3 (high) 0x%08x 0x%08x 0xB4: PM wakeup frame 4 (low) 0x%08x 0x%08x 0xBC: PM wakeup frame 4 (high) 0x%08x 0x%08x 0xC4: Wakeup frame 0 CRC 0x%04x 0xC6: Wakeup frame 1 CRC 0x%04x 0xC8: Wakeup frame 2 CRC 0x%04x 0xCA: Wakeup frame 3 CRC 0x%04x 0xCC: Wakeup frame 4 CRC 0x%04x 0xDA: RX packet maximum size 0x%04x 0x54: Timer interrupt 0x%08x 0x58: Media status 0x%02x 0x59: Config 3 0x%02x 0x5A: Config 4 0x%02x 0x78: PHY parameter 1 0x%08x 0x7C: Twister parameter 0x%08x 0x80: PHY parameter 2 0x%02x 0x82: Low addr of a Tx Desc w/ Tx DMA OK 0x%04x 0x82: MII register 0x%02x 0x84: PM CRC for wakeup frame 0 0x%02x 0x85: PM CRC for wakeup frame 1 0x%02x 0x86: PM CRC for wakeup frame 2 0x%02x 0x87: PM CRC for wakeup frame 3 0x%02x 0x88: PM CRC for wakeup frame 4 0x%02x 0x89: PM CRC for wakeup frame 5 0x%02x 0x8A: PM CRC for wakeup frame 6 0x%02x 0x8B: PM CRC for wakeup frame 7 0x%02x 0x8C: PM wakeup frame 0 0x%08x 0x%08x 0x94: PM wakeup frame 1 0x%08x 0x%08x 0x9C: PM wakeup frame 2 0x%08x 0x%08x 0xA4: PM wakeup frame 3 0x%08x 0x%08x 0xAC: PM wakeup frame 4 0x%08x 0x%08x 0xB4: PM wakeup frame 5 0x%08x 0x%08x 0xBC: PM wakeup frame 6 0x%08x 0x%08x 0xC4: PM wakeup frame 7 0x%08x 0x%08x 0xCC: PM LSB CRC for wakeup frame 0 0x%02x 0xCD: PM LSB CRC for wakeup frame 1 0x%02x 0xCE: PM LSB CRC for wakeup frame 2 0x%02x 0xCF: PM LSB CRC for wakeup frame 3 0x%02x 0xD0: PM LSB CRC for wakeup frame 4 0x%02x 0xD1: PM LSB CRC for wakeup frame 5 0x%02x 0xD2: PM LSB CRC for wakeup frame 6 0x%02x 0xD3: PM LSB CRC for wakeup frame 7 0x%02x 0xD4: Flash memory read/write 0x%08x 0xD8: Config 5 0x%02x 0xE0: C+ Command 0x%04x 0xE2: Interrupt Mitigation 0x%04x TxTimer: %u TxPackets: %u RxTimer: %u RxPackets: %u 0xE4: Rx Ring Addr 0x%08x 0x%08x 0xEC: Early Tx threshold 0x%02x 0xFC: External MII register 0x%08x 0x5E: PCI revision id 0x%02x 0x60: Transmit Status of All Desc (C mode) 0x%04x 0x62: MII Basic Mode Control Register 0x%04x 0x64: MII Basic Mode Status Register 0x%04x 0x66: MII Autonegotiation Advertising 0x%04x 0x68: MII Link Partner Ability 0x%04x 0x6A: MII Expansion 0x%04x 0x6C: MII Disconnect counter 0x%04x 0x6E: MII False carrier sense counter 0x%04x 0x70: MII Nway test 0x%04x 0x72: MII RX_ER counter 0x%04x 0x74: MII CS configuration 0x%04x Address Data ---------- ---- 0x%08x 0x%02x Offset Value ------ ---------- 0x%04x 0x%08x \ H \"$$((, ,004488<=@@DXDHHLLPRTVXZ\ ]` `hHhp4p|@~ %s Control Registers%-32s 0x%08X %s (disabled) Init 0x%08X Value 0x%08X LEDAddr %d %02X%c PCI config ----------%02x:%12s address: %02X %02XPhysical MAC AddressesGenesisYukonYukon-LiteYukon-LPYukon-2 XLYukon ExtremeYukon-2 EC UltraYukon-2 ECYukon-2 FE(Unknown) (rev %d) Bus Management Unit------------------- Status BMU: ----------- Status FIFOStatus levelTX statusISRRx GMAC 1Tx GMAC 1Receive Queue 1Sync Transmit Queue 1Async Transmit Queue 1Receive RAMbuffer 1Sync Transmit RAMbuffer 1Async Transmit RAMbuffer 1Receive RAMbuffer 2Sync Transmit RAMbuffer 2Async Transmit RAMbuffer 21Rx GMAC 2Tx GMAC 2TimerIRQ ModerationBlink SourceReceive MAC FIFO 1Transmit MAC FIFO 1Receive Queue 2Async Transmit Queue 2Sync Transmit Queue 2Receive MAC FIFO 2Transmit MAC FIFO 2Descriptor PollEnd AddressAlmost Full ThreshControl/TestFIFO Flush MaskFIFO Flush ThresholdTruncation ThresholdUpper Pause ThresholdLower Pause ThresholdVLAN TagFIFO Write PointerFIFO Write LevelFIFO Read PointerFIFO Read LevelBuffer control 0x%04X Byte Counter %d Descriptor Address 0x%08X%08X Status 0x%08X Timestamp 0x%08X BMU Control/Status 0x%08X Done 0x%04X Request 0x%08X%08X Csum1 Offset %4d Position %d Csum2 Offset %4d Position %d Csum Start 0x%04X Pos %4d Write %d Register Access Port 0x%02X LED Control/Status 0x%08X Interrupt Source 0x%08X Interrupt Mask 0x%08X Interrupt Hardware Error Source 0x%08X Interrupt Hardware Error Mask 0x%08X Start Address 0x%08X End Address 0x%08X Write Pointer 0x%08X Read Pointer 0x%08X Upper Threshold/Pause Packets 0x%08X Lower Threshold/Pause Packets 0x%08X Upper Threshold/High Priority 0x%08X Lower Threshold/High Priority 0x%08X Packet Counter 0x%08X Level 0x%08X Control 0x%08X Test 0x%02X Control 0x%02X Control/Test 0x%08X Status 0x%04X Control 0x%04X Transmit 0x%04X Receive 0x%04X Transmit flow control 0x%04X Transmit parameter 0x%04X Serial mode 0x%04X Connector type 0x%02X (%c) PMD type 0x%02X (%c) PHY type 0x%02X Chip Id 0x%02X Ram Buffer 0x%02X Descriptor Address 0x%08X%08X Address Counter 0x%08X%08X Current Byte Counter %d Flag & FIFO Address 0x%08X Next 0x%08X Data 0x%08X%08X Csum1 Offset %4d Position %d CSR Receive Queue 1 0x%08X CSR Sync Queue 1 0x%08X CSR Async Queue 1 0x%08X CSR Receive Queue 2 0x%08X CSR Async Queue 2 0x%08X CSR Sync Queue 2 0x%08X Control 0x%08X Last Index 0x%04X Put Index 0x%04X List Address 0x%08X%08X Transmit 1 done index 0x%04X Transmit 2 done index 0x%04X Transmit index threshold 0x%04X Write Pointer 0x%02X Read Pointer 0x%02X Level 0x%02X Watermark 0x%02X ISR Watermark 0x%02X GMAC control 0x%04X GPHY control 0x%04X LINK control 0x%02hX T!`!s!!!!!!!!""%"versioncmd%08x = %08x ethtool_regs %-20s = %04x %-20s = %04x LAN911x Registers index 1, MAC_CR = 0x%08X index 2, ADDRH = 0x%08X index 3, ADDRL = 0x%08X index 4, HASHH = 0x%08X index 5, HASHL = 0x%08X index 6, MII_ACC = 0x%08X index 7, MII_DATA = 0x%08X index 8, FLOW = 0x%08X index 9, VLAN1 = 0x%08X index A, VLAN2 = 0x%08X index B, WUFF = 0x%08X index C, WUCSR = 0x%08X PHY Registers index 7, Reserved = 0x%04X index 8, Reserved = 0x%04X index 9, Reserved = 0x%04X index 10, Reserved = 0x%04X index 11, Reserved = 0x%04X index 12, Reserved = 0x%04X index 13, Reserved = 0x%04X index 14, Reserved = 0x%04X index 15, Reserved = 0x%04X index 19, Reserved = 0x%04X index 20, TSTCNTL = 0x%04X index 21, TSTREAD1 = 0x%04X index 22, TSTREAD2 = 0x%04X index 23, TSTWRITE = 0x%04X index 24, Reserved = 0x%04X index 25, Reserved = 0x%04X index 26, Reserved = 0x%04X offset 0x50, ID_REV = 0x%08X offset 0x54, INT_CFG = 0x%08X offset 0x58, INT_STS = 0x%08X offset 0x5C, INT_EN = 0x%08X offset 0x60, RESERVED = 0x%08X offset 0x64, BYTE_TEST = 0x%08X offset 0x68, FIFO_INT = 0x%08X offset 0x6C, RX_CFG = 0x%08X offset 0x70, TX_CFG = 0x%08X offset 0x74, HW_CFG = 0x%08X offset 0x78, RX_DP_CTRL = 0x%08X offset 0x7C, RX_FIFO_INF = 0x%08X offset 0x80, TX_FIFO_INF = 0x%08X offset 0x84, PMT_CTRL = 0x%08X offset 0x88, GPIO_CFG = 0x%08X offset 0x8C, GPT_CFG = 0x%08X offset 0x90, GPT_CNT = 0x%08X offset 0x94, FPGA_REV = 0x%08X offset 0x98, ENDIAN = 0x%08X offset 0x9C, FREE_RUN = 0x%08X offset 0xA0, RX_DROP = 0x%08X offset 0xA4, MAC_CSR_CMD = 0x%08X offset 0xA8, MAC_CSR_DATA = 0x%08X offset 0xAC, AFC_CFG = 0x%08X offset 0xB0, E2P_CMD = 0x%08X offset 0xB4, E2P_DATA = 0x%08X index 0, Basic Control Reg = 0x%04X index 1, Basic Status Reg = 0x%04X index 2, PHY identifier 1 = 0x%04X index 3, PHY identifier 2 = 0x%04X index 4, Auto Negotiation Advertisement Reg = 0x%04X index 5, Auto Negotiation Link Partner Ability Reg = 0x%04X index 6, Auto Negotiation Expansion Register = 0x%04X index 16, Silicon Revision Reg = 0x%04X index 17, Mode Control/Status Reg = 0x%04X index 18, Special Modes = 0x%04X index 27, Control/Status Indication = 0x%04X index 28, Special internal testability = 0x%04X index 29, Interrupt Source Register = 0x%04X index 30, Interrupt Mask Register = 0x%04X index 31, PHY Special Control/Status Register = 0x%04X ;X*RpSTUVfj,mPtP4Tt0@P'p()`+0,,  .,.H/d001p1205@7 p;@=`>| zAB AG8 AB FX0AB BFxAD !AB AG AB IIE AB IVE WAG TGE( D  F AB DHAB FhAB Ap-AB jAB IAG F% AG FAB EAB BF< AG F\IAB AxAB F+AB I<UAB F0O+AE F`PAB C_AB E8`AB BCXaAB ACxcAB APd]AB ACdAB AC@f\AB AfAB A gAB AC,PhAB ADL iiAB ACliAB AjAB AFPmAB AC`o.AB Fs~AB FvAB F(v AB E ` hohG  @H0ooooo(o,o@04p?P S0ٳ p`XApƲвKp4޲ TCP=˲@<>1F5F9F>FED1FLF>DRFzEFrEF~EFr EFX$EF`(EF~,EGi0EHGu4ELG8ExG